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2.5 v to 5.5 v, 115 a, parallel interface single voltage-output 8-/10-/12-bit dacs ad5330/ad5331/ad5340/ad5341 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2000C2008 analog devices, inc. all rights reserved. features ad5330: single 8-bit dac in 20-lead tssop ad5331: single 10-bit dac in 20-lead tssop ad5340: single 12-bit dac in 24-lead tssop ad5341: single 12-bit dac in 20-lead tssop low power operation: 115 a @ 3 v, 140 a @ 5 v power-down to 80 na @ 3 v, 200 na @ 5 v via pd pin 2.5 v to 5.5 v power supply double-buffered input logic guaranteed monotonic by design over all codes buffered/unbuffered reference input options output range: 0 v to v ref or 0 v to 2 v ref power-on reset to 0 v simultaneous update of dac outputs via ldac pin asynchronous clr facility low power parallel data interface on-chip rail-to-rail output buffer amplifiers temperature range: ?40c to +105c applications portable battery-powered instruments digital gain and offset adjustment programmable voltage and current sources programmable attenuators industrial process control general description the ad5330/ad5331/ad5340/ad5341 1 are single 8-/10-/12- bit dacs. they operate from a 2.5 v to 5.5 v supply consuming just 115 a at 3 v and feature a power-down mode that further reduces the current to 80 na. the devices incorporate an on-chip output buffer that can drive the output to both supply rails, but the ad5330, ad5340, and ad5341 allow a choice of buffered or unbuffered reference input. the ad5330/ad5331/ad5340/ad5341 have a parallel interface. cs selects the device and data is loaded into the input registers on the rising edge of wr . the gain pin allows the output range to be set at 0 v to v ref or 0 v to 2 v ref . input data to the dacs is double-buffered, allowing simultane- ous update of multiple dacs in a system using the ldac pin. an asynchronous clr input is also provided, which resets the contents of the input register and the dac register to all zeros. these devices also incorporate a power-on reset circuit that ensures that the dac output powers on to 0 v and remains there until valid data is written to the device. the ad5330/ad5331/ad5340/ad5341 ar e available in thin shrink small outline packages (tssop). 1 protected by u.s. patent number 5,969,657. functional block diagram buffer 8-bit dac dac register input register interface logic power-down logic buf gain db 7 db 0 . . cs wr clr ldac v ref v dd v out pd gnd ad5330 power-on reset reset 10 9 7 6 13 20 8 1 3 12 4 11 5 0 6852-001 figure 1. ad5330
ad5330/ad5331/ad5340/ad5341 rev. a | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 ac characteristics ........................................................................ 4 timing characteristics ................................................................ 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configurations and function descriptions ........................... 7 terminology .................................................................................... 11 typical performance characteristics ........................................... 13 theory of operation ...................................................................... 17 digital-to-analog section ......................................................... 17 resistor string ............................................................................. 17 dac reference input ................................................................. 17 output amplifier ........................................................................ 17 parallel interface ............................................................................. 18 double-buffered interface ........................................................ 18 clear input ( clr ) ...................................................................... 18 chip select input ( cs ) ............................................................... 18 wr ite input ( wr ) ....................................................................... 18 load dac input ( ldac ) .......................................................... 18 high-byte enable input (hben) ............................................. 18 power-on reset .......................................................................... 18 power-down mode ........................................................................ 19 suggested databus formats .......................................................... 20 applications information .............................................................. 21 typical application circuits ..................................................... 21 driving v dd from the reference voltage ............................... 21 bipolar operation using the ad5330/ad5331/ ad5340/ad5341 ......................................................................... 21 decoding multiple ad5330/ad5331/ ad5340/ad5341 .... 21 programmable current source ................................................ 22 power supply bypassing and grounding ................................ 22 outline dimensions ....................................................................... 24 ordering guide .......................................................................... 25 revision history 2/08rev. 0 to rev. a updated format .................................................................. universal changes to table 4 .......................................................................... 16 replaced driving v dd from the reference voltage section ..... 21 updated outline dimensions ....................................................... 24 changes to ordering guide .......................................................... 25 4/00revision 0: initial version
ad5330/ad5331/ad5340/ad5341 rev. a | page 3 of 28 specifications v dd = 2.5 v to 5.5 v, v ref = 2 v, r l = 2 k to gnd; c l = 200 pf to gnd; all specifications t min to t max , unless otherwise noted. table 1. parameter 1 b version 2 unit conditions/comments min typ max dc performance 3 , 4 ad5330 resolution 8 bits relative accuracy 0.15 1 lsb differential nonlinearity 0.02 0.25 lsb guaranteed monotonic by design over all codes ad5331 resolution 10 bits relative accuracy 0.5 4 lsb differential nonlinearity 0.05 0.5 lsb guaranteed monotonic by design over all codes ad5340/ad5341 resolution 12 bits relative accuracy 2 16 lsbs differential nonlinearity 0.2 1 lsb guaranteed monotonic by design over all codes offset error 0.4 3 % of fsr gain error 0.15 1 % of fsr lower deadband 5 10 60 mv lower deadband exists only if offset error is negative upper deadband 10 60 mv v dd = 5 v; upper deadband exists only if v ref = v dd offset error drift 6 ?12 ppm of fsr/c gain error drift 6 ?5 ppm of fsr/c dc power supply rejection ratio 6 ?60 db v dd = 10% dac reference input 6 v ref input range 1 v dd v buffered reference (ad5330, ad5340, and ad5341) 0.25 v dd v unbuffered reference v ref input impedance >10 m buffered reference (ad5330, ad5340, and ad5341) 180 k unbuffered reference; gain = 1, input impedance = r dac 90 k unbuffered reference; gain = 2, input impedance = r dac reference feedthrough ?90 db frequency = 10 khz output characteristics 6 minimum output voltage 4 , 7 0.001 v min rail-to-rail operation maximum output voltage 4 , 7 v dd ? 0.001 v max dc output impedance 0.5 short-circuit current 25 ma v dd = 5 v 15 ma v dd = 3 v power-up time 2.5 s coming out of power-down mode; v dd = 5 v 5 s coming out of power-down mode; v dd = 3 v logic inputs 6 input current 1 a input low voltage, v il 0.8 v v dd = 5 v 10% 0.6 v v dd = 3 v 10% 0.5 v v dd = 2.5 v input high voltage, v ih 2.4 v v dd = 5 v 10% 2.1 v v dd = 3 v 10% 2.0 v v dd = 2.5 v pin capacitance 3 pf
ad5330/ad5331/ad5340/ad5341 rev. a | page 4 of 28 parameter 1 b version 2 unit conditions/comments min typ max power requirements v dd 2.5 5.5 v i dd (normal mode) dacs active and excluding load currents. unbuffered v dd = 4.5 v to 5.5 v 140 250 a reference, v ih = v dd , v il = gnd v dd = 2.5 v to 3.6 v 115 200 a i dd increases by 50 a at v ref > v dd ? 100 mv. in buffered mode, extra current is (5 + v ref /r dac ) a, where r dac is the resistance of the resistor string. i dd (power-down mode) v dd = 4.5 v to 5.5 v 0.2 1 a v dd = 2.5 v to 3.6 v 0.08 1 a 1 see the terminology section. 2 temperature range: b versio n: ?40c to +105c; typical specifications are at 25c. 3 linearity is tested using a reduced code range: ad5330 (cod e 8 to code 255); ad5331 (code 28 to code 1023); ad5340/ad5341 (cod e 115 to code 4095). 4 dc specifications tested with output unloaded. 5 this corresponds to x codes. x = deadband voltage/lsb size. 6 guaranteed by design and characterization, not production tested. 7 for the amplifier output to reach its minimu m voltage, offset error must be negative . for the amplifier output to reach its ma ximum voltage, v ref = v dd and offset plus gain error must be positive. ac characteristics 1 v dd = 2.5 v to 5.5 v. r l = 2 k to gnd, c l = 200 pf to gnd; all specifications t min to t max , unless otherwise noted. table 2. parameter 2 b version 3 unit conditions/comments min typ max output voltage settling time v ref = 2 v; see figure 29 ad5330 6 8 s ? scale to ? scale change (0x40 to 0xc0) ad5331 7 9 s ? scale to ? scale change (0x100 to 0x300) ad5340 8 10 s ? scale to ? scale change (0x400 to 0xc00) ad5341 8 10 s ? scale to ? scale change (0x400 to 0xc00) slew rate 0.7 v/s major code transition glitch energy 6 nv/s 1 lsb change around major carry digital feedthrough 0.5 nv/s multiplying bandwidth 200 khz v ref = 2 v 0.1 v p-p; unbuffered mode total harmonic distortion ?70 db v ref = 2.5 v 0.1 v p-p; frequency = 10 khz 1 guaranteed by design and characterization, not production tested. 2 see the terminology section. 3 temperature range: b versio n: ?40c to +105c; typical specifications are at 25c.
ad5330/ad5331/ad5340/ad5341 rev. a | page 5 of 28 timing characteristics 1 , 2 , 3 v dd = 2.5 v to 5.5 v, all specifications t min to t max , unless otherwise noted. table 3. parameter limit at t min , t max unit condition/comments t 1 0 ns min cs to wr setup time. t 2 0 ns min cs to wr hold time. t 3 20 ns min wr pulse width. t 4 5 ns min data, gain, buf, hben setup time. t 5 4.5 ns min data, gain, buf, hben hold time. t 6 5 ns min synchronous mode; wr falling to ldac falling. t 7 5 ns min synchronous mode; ldac falling to wr rising. t 8 4.5 ns min synchronous mode; wr rising to ldac rising. t 9 5 ns min asynchronous mode; ldac rising to wr rising. t 10 4.5 ns min asynchronous mode; wr rising to ldac falling. t 11 20 ns min ldac pulse width. t 12 20 ns min clr pulse width. t 13 50 ns min time between wr cycles. 1 guaranteed by design and characterization, not production tested. 2 all input signals are specified with t r = t f = 5 ns (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. 3 see figure 2. cs wr data, gain, buf, hben ldac 1 ldac 2 clr notes: 1 synchronous ldac update mode 2 asynchronous ldac update mode t 1 t 2 t 3 t 4 t 6 t 7 t 9 t 10 t 11 t 12 t 8 t 5 t 13 06852-002 figure 2. parallel interface timing diagram
ad5330/ad5331/ad5340/ad5341 rev. a | page 6 of 28 absolute maximum ratings t a = 25c, unless otherwise noted. table 4. parameter rating v dd to gnd ?0.3 v to +7 v digital input voltage to gnd ?0.3 v to v dd + 0.3 v digital output voltage to gnd ?0.3 v to v dd + 0.3 v reference input voltage to gnd ?0.3 v to v dd + 0.3 v v out to gnd ?0.3 v to v dd + 0.3 v operating temperature range industrial (b version) ?40c to +105c storage temperature range ?65c to +150c junction temperature 150c tssop package power dissipation (t j max C t a )/ ja mw ja thermal impedanc e (20-lead tssop) 1 85c/w ja thermal impedanc e (24-lead tssop) 1 80c/w reflow soldering peak temperature 260c time at peak temperature 20 sec to 40 sec stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution 1 thermal resistance (jedec 4-layer (2s2p) board).
ad5330/ad5331/ad5340/ad5341 rev. a | page 7 of 28 pin configurations and function descriptions buffer 8-bit dac dac register input register interface logic power-down logic buf gain db 7 db 0 . . cs wr clr ldac v ref v dd v out pd gnd ad5330 power-on reset reset 10 9 7 6 13 20 8 1 3 12 4 11 5 06852-003 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 ldac gain wr cs gnd buf v ref v out clr nc = no connect nc db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 v dd pd top view (not to scale) ad5330 8-bit 06852-004 figure 3. ad5330 functional block diagram figure 4. ad5330 pin configuration table 5. ad5330 pin function descriptions pin no. mnemonic description 1 buf buffer control pin. this pin controls whether the reference input to the dac is buffered or unbuffered. 2 nc no connect. 3 v ref reference input. 4 v out output of dac. buffered output with rail-to-rail operation. 5 gnd ground reference point for all circuitry on the part. 6 cs active low chip select input. this is used in conjunction with wr to write data to the parallel interface. 7 wr active low write input. this is used in conjunction with cs to write data to the parallel interface. 8 gain gain control pin. this controls whet her the output range from the dac is 0 v to v ref or 0 v to 2 v ref . 9 clr asynchronous active low control input that clears all input registers and dac registers to zero. 10 ldac active low control input that updates the dac regist ers with the contents of the input registers. 11 pd power-down pin. this active low control pin puts the dac into power-down mode. 12 v dd power supply input. these parts can operate from 2.5 v to 5.5 v and the supply should be decoupled with a 10 f capacitor in parallel with a 0.1 f capacitor to gnd. 13 to 20 db 0 to db 7 eight parallel data inputs. db 7 is the msb of these eight bits.
ad5330/ad5331/ad5340/ad5341 rev. a | page 8 of 28 buffer 10-bit dac dac register input register interface logic power-down logic db 8 db 7 db 0 . . cs wr clr ldac v ref v dd v out pd gnd ad5331 power-on reset reset 10 9 7 6 13 20 1 db 9 2 gain 8 3 12 4 11 5 06852-005 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 ldac gain wr cs gnd v ref v out clr db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 v dd pd top view (not to scale) ad5331 10-bit db 8 db 9 06852-006 figure 5. ad5331 functional block diagram figure 6. ad5331 pin configuration table 6. ad5331 pin function descriptions pin no. mnemonic description 1 db 8 parallel data input. 2 db 9 most significant bit of parallel data input. 3 v ref unbuffered reference input. 4 v out output of dac. buffered output with rail-to-rail operation. 5 gnd ground reference point for all circuitry on the part. 6 cs active low chip select input. th is is used in conjunction with wr to write data to the parallel interface. 7 wr active low write input. this is used in conjunction with cs to write data to the parallel interface. 8 gain gain control pin. this controls whet her the output range from the dac is 0 v to v ref or 0 v to 2 v ref . 9 clr active low control input that clears all input registers and dac registers to zero. 10 ldac active low control input that updates the dac regist ers with the contents of the input registers. 11 pd power-down pin. this active low control pin puts the dac into power-down mode. 12 v dd power supply input. these parts can operate from 2.5 v to 5.5 v and the supply should be decoupled with a 10 f capacitor in parallel with a 0.1 f capacitor to gnd. 13 to 20 db 0 to db 7 eight parallel data inputs.
ad5330/ad5331/ad5340/ad5341 rev. a | page 9 of 28 buffer 12-bit dac dac register input register power-down logic cs wr clr ldac v ref v dd v out pd gnd ad5340 power-on reset reset 12 11 9 8 4 14 5 13 7 06852-007 db 10 db 9 db 0 . . 15 24 1 db 11 2 buf 3 gain 10 interface logic 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 db 10 pd v dd db 0 db 1 db 2 db 7 db 6 db 3 db 4 db 5 12-bit ad5340 top view (not to scale) db 8 db 9 db 11 ldac gnd buf v out nc v ref cs wr gain clr 06852-008 figure 7. ad5340 functional block diagram figure 8. ad5340 pin configuration table 7. ad5340 pin function descriptions pin no. mnemonic description 1 db 10 parallel data input. 2 db 11 most significant bit of parallel data input. 3 buf buffer control pin. this pin controls whether the reference input to the dac is buffered or unbuffered. 4 v ref reference input. 5 v out output of dac. buffered output with rail-to-rail operation. 6 nc no connect. 7 gnd ground reference point for all circuitry on the part. 8 cs active low chip select input. this is used in conjunction with wr to write data to the parallel interface. 9 wr active low write input. this is used in conjunction with cs to write data to the parallel interface. 10 gain gain control pin. this controls whet her the output range from the dac is 0 v to v ref or 0 v to 2 v ref . 11 clr asynchronous active low control input that clears all input registers and dac registers to zero. 12 ldac active low control input that updates the dac regist ers with the contents of the input registers. 13 pd power-down pin. this active low control pin puts the dac into power-down mode. 14 v dd power supply input. these parts can operate from 2.5 v to 5.5 v and the supply should be decoupled with a 10 f capacitor in parallel with a 0.1 f capacitor to gnd. 15 to 24 db 0 to db 9 ten parallel data inputs.
ad5330/ad5331/ad5340/ad5341 rev. a | page 10 of 28 buffer 12-bit dac dac register low byte register interface logic power-down logic buf db 7 db 0 . . hben cs wr clr ldac v ref v dd v out pd gnd ad5341 power-on reset reset 9 7 6 1 13 20 2 gain 8 3 12 4 11 5 high byte register 10 06852-009 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 ldac gain wr cs gnd v ref v out clr db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 v dd pd top view (not to scale) ad5341 10-bit hben buf 06852-010 figure 9. ad5341 functional block diagram figure 10. ad5341 pin configuration table 8. ad5341 pin function descriptions pin no. mnemonic description 1 hben high byte enable pin. this pin is used when writing to the device to determine if data is written to the high byte register or the low byte register. 2 buf buffer control pin. this pin controls whether the reference input to the dac is buffered or unbuffered. 3 v ref reference input. 4 v out output of dac. buffered output with rail-to-rail operation. 5 gnd ground reference point for all circuitry on the part. 6 cs active low chip select input. this is used in conjunction with wr to write data to the parallel interface. 7 wr active low write input. this is used in conjunction with cs to write data to the parallel interface. 8 gain gain control pin. this controls whet her the output range from the dac is 0 v to v ref or 0 v to 2 v ref . 9 clr asynchronous active low control input that clears all input registers and dac registers to zero. 10 ldac active low control input that updates the dac regist ers with the contents of the input registers. 11 pd power-down pin. this active low control pin puts the dac into power-down mode. 12 v dd power supply input. these parts can operate from 2.5 v to 5.5 v and the supply should be decoupled with a 10 f capacitor in parallel with a 0.1 f capacitor to gnd. 13 to 20 db 0 to db 7 eight parallel data inputs. db 7 is the msb of these eight bits.
ad5330/ad5331/ad5340/ad5341 rev. a | page 11 of 28 terminology output voltage dac code positive offset gain error and offset error actual ideal 06852-012 relative accuracy or integral nonlinearity (inl) for the dac, relative accuracy or inl is a measure of the maximum deviation, in lsbs, from a straight line passing through the actual endpoints of the dac transfer function. typical inl vs. code plots can be seen in figure 14 , figure 15 , and figure 16 . differential nonlinearity (dnl) dnl is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures mono- tonicity. this dac is guaranteed monotonic by design. typical dnl vs. code plots can be seen in figure 17 , figure 18 , and figure 19 . gain error this is a measure of the span error of the dac (including any error in the gain of the buffer amplifier). it is the deviation in slope of the actual dac transfer characteristic from the ideal, expressed as a percentage of the full-scale range. this is illustrated in figure 11 . figure 12. positive offset error and gain error output voltage dac code negative offset gain error and offset error actual ideal amplifier footroom (~1mv) negative offset deadband codes 0 6852-013 offset error this is a measure of the offset error of the dac and the output amplifier. it is expressed as a percentage of the full-scale range. if the offset voltage is positive, the output voltage is still positive at zero input code. this is shown in figure 12 . because the dacs operate from a single supply, a negative offset cannot appear at the output of the buffer amplifier. instead, there is a code close to zero at which the amplifier output saturates (amplifier footroom). below this code, there is a deadband over which the output voltage does not change. this is illustrated in figure 13 . output v oltage dac code positive gain error actual ideal negative gain error 06852-011 figure 13. negative offset error and gain error figure 11. gain error
ad5330/ad5331/ad5340/ad5341 rev. a | page 12 of 28 offset error drift this is a measure of the change in offset error with changes in temperature. it is expressed in (ppm of full-scale range)/c. gain error drift this is a measure of the change in gain error with changes in temperature. it is expressed in (ppm of full-scale range)/c. power-supply rejection ratio (psrr) this indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v out to a change in v dd for full-scale output of the dac. it is measured in decibels. v ref is held at 2 v and v dd is varied 10%. reference feedthrough this is the ratio of the amplitude of the signal at the dac output to the reference input when the dac output is not being updated (that is, ldac is high). it is expressed in decibels. major-code transition glitch energy major-code transition glitch energy is the energy of the impulse injected into the analog output when the dac changes state. it is normally specified as the area of the glitch in nv/s and is measured when the digital code is changed by 1 lsb at the major carry transition (011 11 to 100 00 or 100 00 to 011 11). digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital input pins of the device; it is measured when the dac is not being written to ( cs held high). it is specified in nv/s and is measured with a full- scale change on the digital input pins, that is, from all 0s to all 1s and vice versa. multiplying bandwidth the amplifiers within the dac have a finite bandwidth. the multiplying bandwidth is a measure of this. a sine wave on the reference (with a full-scale code loaded to the dac) appears on the output. the multiplying bandwidth is the frequency at which the output amplitude falls to 3 db below the input. total harmonic distortion (thd) this is the difference between an ideal sine wave and its atte- nuated version using the dac. the sine wave is used as the reference for the dac and thd is a measure of the harmonics present on the dac output. it is measured in decibels.
ad5330/ad5331/ad5340/ad5341 rev. a | page 13 of 28 typical performance characteristics 1.0 0.5 0 ?0.5 ?1.0 0 50 100 150 200 250 inl error (lsbs) code t a = 25c v dd = 5v 06852-015 figure 14. ad5330 typical inl plot 3 2 1 0 ?1 ?3 ?2 0 200 400 500 800 1000 inl error (lsbs) code t a = 25c v dd = 5v 06852-016 figure 15. ad5331 typical inl plot 12 8 4 0 ?12 ?8 ?4 0 1000 2000 3000 4000 inl error (lsbs) code t a = 25c v dd = 5v 06852-017 figure 16. ad5340/ad5341 typical inl plot 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 0 50 100 150 200 250 dnl error (lsbs) code t a = 25c v dd = 5v 06852-018 figure 17. ad5330 typical dnl plot 0.6 0.2 0.4 0 ?0.2 ?0.4 ?0.6 0 200 400 600 800 1000 dnl error (lsbs) code t a = 25c v dd = 5v 0 6852-019 figure 18. ad5331 typical dnl plot 1.0 0.5 0 ?0.5 ?1.0 0 1000 2000 3000 4000 dnl error (lsbs) code t a = 25c v dd = 5v 06852-020 figure 19. ad5340/ad5341 typical dnl plot
ad5330/ad5331/ad5340/ad5341 rev. a | page 14 of 28 1.00 0.50 0.75 0 ?0.50 0.25 ?0.25 ?0.75 ?1.00 2345 error (lsbs) v ref (v) max inl max dnl min dnl min inl t a = 25c v dd = 5v 06852-021 figure 20. ad5330 inl and dnl error vs. v ref v dd = 5v v ref = 3v 1.00 0.50 0.75 0 ?0.50 0.25 ?0.25 ?0.75 ?1.00 ?40 0 40 80 120 error (lsbs) temperature (c) max inl max dnl min dnl min inl 06852-022 figure 21. ad5330 inl error and dnl error vs. temperature v dd = 5v v ref = 2v 1.0 0.5 0 ?0.5 ?1.0 ?40 0 40 80 120 error (%) temperature (c) gain error offset error 0 6852-023 figure 22. ad5330 offset error and gain error vs. temperature gain error offset error ?0.1 0 0.1 0.2 ?0.2 ?0.3 ?0.4 ?0.5 ?0.6 0123456 error (%) v dd (v) t a = 25c v ref = 2v 06852-024 figure 23. offset error and gain error vs. v dd 5 0 1 2 3 4 0123456 v out (v) sink/source current (ma) 5v source 3v source 3v sink 5v sink 06852-025 figure 24. v out source and sink current capability 300 0 50 100 150 200 250 zero-scale full-scale i dd (a) dac code t a = 25c v ref = 2v v dd = 5.5v v dd = 3.6v 06852-026 figure 25. supply current vs. dac code
ad5330/ad5331/ad5340/ad5341 rev. a | page 15 of 28 300 t a = 25c 200 100 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 i dd (a) v dd (v) 06852-027 figure 26. supply current vs. supply voltage 0.5 t a = 25c 0 0.1 0.2 0.3 0.4 2.5 3.0 3.5 4.0 4.5 5.0 5.5 i dd (a) v dd (v) 06852-028 figure 27. power-down current vs. supply voltage i dd (a) v logic (v) 1800 t a = 25c 0 200 400 600 800 1000 1200 1400 1600 012345 v dd = 5v v dd = 3v 06852-029 figure 28. supply current vs. logic input voltage clk ch1 1v ch2 5v t a = 25c v dd = 5v v out time base = 5s/div 06852-030 figure 29. half-scale settling (? to ? scale code change) ch1 2v ch2 2 00m v time base = 200s/div t a = 25c v dd = 5v v ref = 2v v dd v out a 06852-031 figure 30. power-on reset to 0 v ch1 500mv ch2 5v time base = 1s/div t a = 25c v dd = 5v v ref = 2v v out a pd 06852-032 figure 31. exiting power-down to midscale
ad5330/ad5331/ad5340/ad5341 rev. a | page 16 of 28 10 ?60 ?50 ?40 ?30 ?20 ?10 0 0.01 0.1 1 100 10 10k 1k (db) frequency (khz) 06852-035 80 90 100 110 120 130 140 150 160 170 190180 200 frequency i dd (a) v dd = 3v v dd = 5v 06852-033 figure 32. i dd histogram with v dd = 3 v and v dd = 5 v figure 34. multiplying bandwidth (small-signal frequency response) ?0.2 0 0.2 0.4 012 4 35 full-scale error (%fsr) v ref (v) t a = 25c v dd = 5v 06852-036 250ns/div 0.903 0.904 0.905 0.906 0.907 0.908 0.909 0.910 0.911 0.912 0.913 0.914 0.915 0.916 0.917 volts 0 6852-034 figure 33. ad5340 major-code transition glitch energy figure 35. full-scale error vs. v ref
ad5330/ad5331/ad5340/ad5341 rev. a | page 17 of 28 theory of operation the ad5330/ad5331/ad5340/ad5341 are single resistor- string dacs fabricated on a cmos process with resolutions of 8, 10, and 12 bits, respectively. they are written to using a parallel interface. they operate from single supplies of 2.5 v to 5.5 v and the output buffer amplifiers offer rail-to-rail output swing. the ad5330, ad5340, and ad5341 have a reference input that can be buffered to draw virtually no current from the reference source. the reference input of the ad5331 is unbuffered. the devices have a power-down feature that reduces current consumption to only 80 na @ 3 v. digital-to-analog section the architecture of one dac channel consists of a reference buffer and a resistor-string dac followed by an output buffer amplifier. the voltage at the v ref pin provides the reference voltage for the dac. figure 36 shows a block diagram of the dac architecture. because the input coding to the dac is straight binary, the ideal output voltage is given by gain d vv n ref out = 2 where: d is the decimal equivalent of the binary code, which is loaded to the dac register: 0 to 255 for ad5330 (8 bits) 0 to 1023 for ad5331 (10 bits) 0 to 4095 for ad5340/ad5341 (12 bits) n is the dac resolution. gain is the output amplifier gain (1 or 2). gain v ref v out buf dac register input register resistor string output buffer amplifier reference buffer 06852-037 figure 36. single dac channel architecture resistor string the resistor-string section is shown in figure 37. it is simply a string of resistors, each of value r. the digital code loaded to the dac register determines at what node on the string the voltage is tapped off to be fed into the output amplifier. the voltage is tapped off by closing one of the switches connecting the string to the amplifier. because it is a string of resistors, it is guaranteed monotonic. to output amplifier r r r r r v ref 06852-038 figure 37. resistor string dac reference input there is a reference input pin for the dac. the reference input is buffered on the ad5330, ad5340, and ad5341 but can be configured as unbuffered also. the reference input of the ad5331 is unbuffered. the buffered/unbuffered option is controlled by the buf pin. in buffered mode (buf = 1), the current drawn from an external reference voltage is virtually zero because the impedance is at least 10 m. the reference input range is 1 v to 5 v with a 5 v supply. in unbuffered mode (buf = 0), the user can have a reference voltage as low as 0.25 v and as high as v dd because there is no restriction due to headroom and footroom of the reference amplifier. the impedance is still large at typically 180 k for 0 v to v ref mode and 90 k for 0 v to 2 v ref mode. if there is an external buffered reference (for example, ref192 ), there is no need to use the on-chip buffer. output amplifier the output buffer amplifier is capable of generating output voltages to within 1 mv of either rail. its actual range depends on v ref , gain, the load on v out , and offset error. if a gain of 1 is selected (gain = 0), the output range is 0.001 v to v ref . if a gain of 2 is selected (gain = 1), the output range is 0.001 v to 2 v ref . however, because of clamping, the maximum output is limited to v dd C 0.001 v. the output amplifier is capable of driving a load of 2 k to gnd or 2 k to v dd in parallel with 500 pf to gnd or 500 pf to v dd . the source and sink capabilities of the output amplifier can be seen in figure 24. the slew rate is 0.7 v/s with a half-scale settling time to 0.5 lsb (at eight bits) of 6 s with the output unloaded (see figure 29).
ad5330/ad5331/ad5340/ad5341 rev. a | page 18 of 28 parallel interface the ad5330, ad5331, and ad5340 load their data as a single 8-, 10-, or 12-bit word, while the ad5341 loads data as a low byte of eight bits and a high byte containing four bits. double-buffered interface the ad5330/ad5331/ad5340/ad5341 dacs all have double- buffered interfaces consisting of an input register and a dac register. dac data, buf, and gain inputs are written to the input register under the control of chip select ( cs ) and write ( wr ). access to the dac register is controlled by the ldac function. when ldac is high, the dac register is latched and the input register may change state without affecting the contents of the dac register. however, when ldac is brought low, the dac register becomes transparent and the contents of the input register are transferred to it. the gain and buffer control signals are also double-buffered and are only updated when ldac is taken low. double-buffering is also useful where the dac data is loaded in two bytes, as in the ad5341, because it allows the whole data word to be assembled in parallel before updating the dac register. this prevents spurious outputs that can occur if the dac register is updated with only the high byte or the low byte. these parts contain an extra feature whereby the dac register is not updated unless its input register has been updated since the last time that ldac was brought low. normally, when ldac is brought low, the dac register is filled with the contents of the input register. in the case of the ad5330/ ad5331/ad5340/ad5341, the parts only update the dac register if the input register has been changed since the last time the dac register was updated. this removes unnecessary crosstalk. clear input ( clr ) clr is an active low, asynchronous clear that resets the input and dac registers. chip select input ( cs ) cs is an active low input that selects the device. write input ( wr ) wr is an active low input that controls writing of data to the device. data is latched into the input register on the rising edge of wr . load dac input ( ldac ) ldac transfers data from the input register to the dac register (and therefore updates the outputs). use of the ldac function enables double-buffering of the dac data, gain, and buf. there are two ldac modes: synchronous mode and asynchronous mode. in synchronous mode, the dac register is updated after new data is read in on the rising edge of the wr input. ldac can be tied permanently low or pulsed, as shown in . figure 2 in asynchronous mode, the outputs are not updated at the same time that the input register is written to. when ldac goes low, the dac register is updated with the contents of the input register. high byte enable input (hben) high byte enable is a control input on the ad5341 only. it determines if data is written to the high byte input register or the low byte input register. the low data byte of the ad5341 consists of data bits [0:7] at the data inputs db 0 to db 7 , whereas the high byte consists of data bits [8:11] at the data inputs db 0 to db 3 , as shown in figure 38 . db 4 to db 7 are ignored during a high byte write, but they can be used for data to set up the reference input as buffered/ unbuffered, and buffer amplifier gain (see figure 42 ). db 8 db 9 xx high byte low byte x = unused bit db 0 db 1 db 2 db 3 db 4 db 5 db 6 db 7 xx db 10 db 11 06852-039 figure 38. data format for ad5341 power-on reset t he ad5330/ad5331/ad5340/ad5341 are provided with a power-on reset function, so that they power up in a defined state. the power-on state is ? normal operation ? reference input unbuffered ? 0 v to v ref output range ? output voltage set to 0 v both input and dac registers are filled with zeros and remain as such until a valid write sequence is made to the device. this is particularly useful in applications where it is important to know the state of the dac outputs while the device is powering up.
ad5330/ad5331/ad5340/ad5341 rev. a | page 19 of 28 power-down mode the ad5330/ad5331/ad5340/ad5341 have low power consumption, dissipating only 0.35 mw with a 3 v supply and 0.7 mw with a 5 v supply. power consumption can be further reduced when the dac is not in use by putting it into power- down mode, which is selected by taking pin pd low. when the pd pin is high, the dac works normally with a typical power consumption of 140 a at 5 v (115 a at 3 v). in power-down mode, however, the supply current falls to 200 na at 5 v (80 na at 3 v) when the dac is powered down. not only does the supply current drop, but the output stage is also internally switched from the output of the amplifier, making it open-circuit. this has the advantage that the output is three-state while the part is in power-down mode and provides a defined input condition for whatever is connected to the output of the dac amplifier. the output stage is illustrated in . figure 39 resistor string dac power-down circuitry amplifier v out 06852-040 figure 39. output stage during power-down the bias generator, the output amplifier, the resistor string, and all other associated linear circuitry are shut down when the power-down mode is activated. however, the contents of the registers are unaffected when in power-down. the time to exit power-down is typically 2.5 s for v dd = 5 v and 5 s when v dd = 3 v. this is the time from a rising edge on the pd pin to when the output voltage deviates from its power-down voltage (see ). figure 31 table 9. ad5330/ad5331/ad5340 truth table 1 clr ldac cs wr function 1 1 1 x no data transfer 1 1 x 1 no data transfer 0 x x x clear all registers 1 1 0 01 load input register 1 0 0 01 load input register and dac register 1 0 x x update dac register 1 x = dont care. table 10. ad5341 truth table 1 clr ldac cs wr hben function 1 1 1 x x no data transfer 1 1 x 1 x no data transfer 0 x x x x clear all registers 1 1 0 01 0 load low byte input register 1 1 0 01 1 load high byte input register 1 0 0 01 0 load low byte input register and dac register 1 0 0 01 1 load high byte input register and dac register 1 0 x x x update dac register 1 x = dont care.
ad5330/ad5331/ad5340/ad5341 rev. a | page 20 of 28 suggested databus formats in most applications, gain and buf are hard-wired. however, if more flexibility is required, they can be included in a databus. this enables the user to software program gain, giving the option of doubling the resolution in the lower half of the dac range. in a bused system, gain and buf can be treated as data inputs because they are written to the device during a write operation and take effect when ldac is taken low. this means that the reference buffers and the output amplifier gain of multiple dac devices can be controlled using common gain and buf lines. in the case of the ad5330, this means that the databus must be wider than eight bits. the ad5331 and ad5340 databuses must be at least 10 bits and 12 bits wide, respectively, and are best suited to a 16-bit databus system. examples of data formats for putting gain and buf on a 16-bit databus are shown in figure 40 . note that any unused bits above the actual dac data can be used for buf and gain. dac devices can be controlled using common gain and buf lines. ad5331 db 0 db 1 db 2 db 3 db 4 db 5 db 6 db 7 gain xxxx x x buf ad5330 ad5340 x = unused bit db 0 db 1 db 2 db 3 db 4 db 5 db 6 db 7 gain x xxx buf db 9 db 8 xx db 0 db 1 db 2 db 3 db 4 db 5 db 6 db 7 gain buf db 9 db 8 db 10 db 11 06852-041 figure 40. gain and buf data on a 16-bit bus the ad5341 is a 12-bit device that uses byte load, so only four bits of the high byte are actually used as data. two of the unused bits can be used for gain and buf data by connecting them to the gain and buf inputs; for example, bit 6 and bit 7, as shown in figure 41 and figure 42 . data inputs buf gain ldac clr cs wr hben ad5341 db 7 db 6 8-bit data bus 0 6852-042 figure 41. ad5341 data format for byte load with gain and buf data on 8-bit bus in this case, the low byte is written to first in a write operation with hben = 0. bit 6 and bit 7 of dac data are written into gain and buf registers but have no effect. the high byte is then written to. only the lower four bits of data are written into the dac high byte register, so bit 6 and bit 7 can be gain and buf data. ldac is used to update the dac, gain, and buf values. db 8 db 9 high byte low byte x = unused bit db 0 db 1 db 2 db 3 db 4 db 5 db 6 db 7 xx db 10 db 11 buf gain 06852-043 figure 42. ad5341 with gain and buf data on 8-bit bus
ad5330/ad5331/ad5340/ad5341 rev. a | page 21 of 28 applications information typical application circuits the ad5330/ad5331/ad5340/ad5341 can be used with a wide range of reference voltages, especially if the reference inputs are configured to be unbuffered, in which case the devices offer full, one-quadrant multiplying capability over a reference range of 0.25 v to v dd . more typically, these devices can be used with a fixed, precision reference voltage. figure 43 shows a typical setup for the devices when using an external reference connected to the unbuffered reference inputs. if the reference inputs are unbuffered, the reference input range is from 0.25 v to v dd , but if the on-chip reference buffers are used, the reference range is reduced. suitable references for 5 v operation are the ad780 and ref192 . for 2.5 v operation, a suitable external reference is the ad589 , a 1.23 v band gap reference. ad5330/ad5331/ ad5340/ad5341 v out v dd = 2.5v to 5.5 v v dd gnd v ref gnd ext ref + 0.1f 10f v out v in ad780/ref192 with v dd = 5v or a d589 with v dd = 2.5v 06852-044 figure 43. ad5330/ad5331/ad5340/ad5341 using external reference driving v dd from the reference voltage if an output range of 0 v to v dd is required, the simplest solution is to connect the reference inputs to v dd . because this supply may not be very accurate and may be noisy, the devices can be powered from the reference voltage, for example using a 5 v reference such as the adp667, as shown in figure 44 . ad5330/ad5331/ ad5340/ad5341 gnd shdn v out adp667 vset 6v to 16 v v out v dd v in gnd v ref + 0.1f 0.1f 10f 06852-045 figure 44. using an adp667 as power and reference to ad5330/ad5331/ad5340/ad5341 bipolar operation using the ad5330/ad5331/ ad5340/ad5341 the ad5330/ad5331/ad5340/ad5341 are designed for single-supply operation, but bipolar operation is achievable using the circuit shown in figure 45 . the circuit shown has been configured to achieve an output voltage range of C5 v < v o < +5 v. rail-to-rail operation at the amplifier output is achievable using an ad820 or op295 as the output amplifier. the output voltage for any input code can be calculated as follows: v o = [(1 + r4 / r3 ) ( r2 /( r1 + r2 ) (2 v ref d /2 n )] C r4 v ref / r3 where: d is the decimal equivalent of the code loaded to the dac. n is the dac resolution. v ref is the reference voltage input. with: v ref = 2.5 v. r1 = r3 = 10 k. r2 = r4 = 20 k and v dd = 5 v. v o = (10 d/2 n ) ? 5. v dd = 5 v + 0.1f 10f r2 20k? r1 10k? r3 10k ? r4 20k ? gnd v o = 5v +5v ?5v ad5330/ad5331/ ad5340/ad5341 v ref v out v dd gnd ext ref v out v in ad780/ref192 with v dd = 5v or ad589 with v dd = 2.5v 0.1f 06852-046 figure 45. bipolar operation using the ad5330/ad5331/ad5340/ad5341 decoding multiple ad5330/ad5331/ ad5340/ad5341 the cs pin on these devices can be used in applications to decode a number of dacs. in this application, all dacs in the system receive the same data and wr pulses, but only cs to one of the dacs is active at any one time, so data is only written to the dac whose cs is low. if multiple ad5341s are being used, a common hben line is also required to determine if the data is written to the high byte or low byte register of the selected dac. the 74hc139 is used as a 2-line to 4-line decoder to address any of the dacs in the system. to prevent timing errors, the enable input should be brought to its inactive state while the coded address inputs are changing state. figure 46 shows a diagram of a typical setup for decoding multiple devices in a system. once data has been written sequentially to all dacs in
ad5330/ad5331/ad5340/ad5341 rev. a | page 22 of 28 a system, all the dacs can be updated simultaneously using a common ldac line. a common clr line can also be used to reset all dac outputs to zero. enable coded a ddress g1 a1 b1 v dd v cc 74hc139 dgnd 1y0 1y1 1y2 1y3 data inputs data bus *ad5341 only ldac clr cs hben* ad5330/ad5331/ ad5340/ad5341 wr ldac clr hben* wr data inputs ldac clr cs hben* ad5330/ad5331/ ad5340/ad5341 wr data inputs ldac clr cs hben* ad5330/ad5331/ ad5340/ad5341 wr data inputs ldac clr cs hben* ad5330/ad5331/ ad5340/ad5341 wr 06852-047 figure 46. decoding multiple dac devices programmable current source figure 47 shows the ad5330/ad5331/ad5340/ad5341 used as the control element of a programmable current source. in this example, the full-scale current is set to 1 ma. the output voltage from the dac is applied across the current setting resistor of 4.7 k in series with the 470 adjustment poten- tiometer, which gives an adjustment of about 5%. suitable transistors to place in the feedback loop of the amplifier include the bc107 and the 2n3904, which enable the current source to operate from a minimum v source of 6 v. the operating range is determined by the operating characteristics of the transistor. suitable amplifiers include the ad820 and the op295 , both having rail-to-rail operation on their outputs. the current for any digital input code and resistor value can be calculated as follows: ma )2( r d vgi n ref = where: g is the gain of the buffer amplifier (1 or 2). d is the digital equivalent of the digital input code. n is the dac resolution (8, 10, or 12 bits). r is the sum of the resistor plus adjustment potentiometer in kilo ohms. ad5330/ad5331/ ad5340/ad5341 v dd = 5 v 4.7k ? 5v 470 ? load v source v ref v dd gnd v out ad820/ op295 + 0.1f 10f 0.1f gnd ext ref v out v in ad780/ref192 with v dd = 5v 06852-048 figure 47. programmable current source power supply bypassing and grounding in any circuit where accuracy is important, careful consid- eration of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the ad5330/ad5331/ad5340/ad5341 are mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. if the device is in a system where multiple devices require an agnd- to-dgnd connection, the connection should be made at one point only. the star ground point should be established as closely as possible to the device. the ad5330/ad5331/ ad5340/ad5341 should have ample supply bypassing of 10 f in parallel with 0.1 f on the supply located as close to the package as possible, ideally right up against the device. the 10 f capacitors are the tantalum bead type. the 0.1 f capacitor should have low effective series resistance (esr) and effective series inductance (esi), like the common ceramic types that provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. the power supply lines of the device should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough through the board. a microstrip technique is by far the best, but not always possible with a double-sided board. in this technique, the component side of the board is dedicated to the ground plane while signal traces are placed on the solder side.
ad5330/ad5331/ad5340/ad5341 rev. a | page 23 of 28 table 11. overview of ad53xx parallel devices part no. resolution bits dnl no. of v ref pins settling time additional pin functions package no. of pins buf gain hben clr singles ad5330 8 0.25 1 6 s buf gain clr tssop 20 ad5331 10 0.5 1 7 s gain clr tssop 20 ad5340 12 1.0 1 8 s buf gain clr tssop 24 ad5341 12 1.0 1 8 s buf gain hben clr tssop 20 duals ad5332 8 0.25 2 6 s clr tssop 20 ad5333 10 0.5 2 7 s buf gain clr tssop 24 ad5342 12 1.0 2 8 s buf gain clr tssop 28 ad5343 12 1.0 1 8 s hben clr tssop 20 quads ad5334 8 0.25 2 6 s gain clr tssop 24 ad5335 10 0.5 2 7 s hben clr tssop 24 ad5336 10 0.5 4 7 s gain clr tssop 28 ad5344 12 1.0 4 8 s tssop 28 table 12. overview of ad53xx serial devices part no. resolution bits no. of dacs dnl interface settling time package no of pins singles ad5300 8 1 0.25 spi 4 s sot-23, msop 6, 8 ad5310 10 1 0.5 spi 6 s sot-23, msop 6, 8 ad5320 12 1 1.0 spi 8 s sot-23, msop 6, 8 ad5301 8 1 0.25 2-wire 6 s sot-23, msop 6, 8 ad5311 10 1 0.5 2-wire 7 s sot-23, msop 6, 8 ad5321 12 1 1.0 2-wire 8 s sot-23, msop 6, 8 duals ad5302 8 2 0.25 spi 6 s msop 10 ad5312 10 2 0.5 spi 7 s msop 10 ad5322 12 2 1.0 spi 8 s msop 10 ad5303 8 2 0.25 spi 6 s tssop 16 ad5313 10 2 0.5 spi 7 s tssop 16 ad5323 12 2 1.0 spi 8 s tssop 16 quads ad5304 8 4 0.25 spi 6 s msop, lfcsp 10 ad5314 10 4 0.5 spi 7 s msop, lfcsp 10 ad5324 12 4 1.0 spi 8 s msop, lfcsp 10 ad5305 8 4 0.25 2-wire 6 s msop 10 ad5315 10 4 0.5 2-wire 7 s msop 10 ad5325 12 4 1.0 2-wire 8 s msop 10 ad5306 8 4 0.25 2-wire 6 s tssop 16 ad5316 10 4 0.5 2-wire 7 s tssop 16 ad5326 12 4 1.0 2-wire 8 s tssop 16 ad5307 8 4 0.25 spi 6 s tssop 16 ad5317 10 4 0.5 spi 7 s tssop 16 ad5327 12 4 1.0 spi 8 s tssop 16
ad5330/ad5331/ad5340/ad5341 rev. a | page 24 of 28 outline dimensions compliant to jedec standards mo-153-ac 20 1 11 10 6.40 bsc 4.50 4.40 4.30 pin 1 6.60 6.50 6.40 seating plane 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 coplanarit y 0.10 figure 48. 20-lead thin shrink small outline package [tssop] (ru-20) dimensions shown in millimeters 24 13 12 1 6.40 bsc 4.50 4.40 4.30 pin 1 7.90 7.80 7.70 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 seating plane 0.10 coplanarity compliant to jedec standards mo-153-ad figure 49. 24-lead thin shrink small outline package [tssop] (ru-24) dimensions shown in millimeters
ad5330/ad5331/ad5340/ad5341 rev. a | page 25 of 28 ordering guide model temperature range package description package option ad5330bru C40c to +105c 20-lead thin shrink small outline package [tssop] ru-20 AD5330BRU-REEL C40c to +105c 20-lead thin shrink small outline package [tssop] ru-20 AD5330BRU-REEL7 C40c to +105c 20-lead thin shrink small outline package [tssop] ru-20 ad5330bruz 1 C40c to +105c 20-lead thin shrink small outline package [tssop] ru-20 ad5330bruz-reel 1 C40c to +105c 20-lead thin shrink small outline package [tssop] ru-20 ad5330bruz-reel7 1 C40c to +105c 20-lead thin shrink small outline package [tssop] ru-20 ad5331bru C40c to +105c 20-lead thin shrink small outline package [tssop] ru-20 ad5331bru-reel C40c to +105c 20-lead thin shrink small outline package [tssop] ru-20 ad5331bru-reel7 C40c to +105c 20-lead thin shrink small outline package [tssop] ru-20 ad5331bruz 1 C40c to +105c 20-lead thin shrink small outline package [tssop] ru-20 ad5331bruz-reel 1 C40c to +105c 20-lead thin shrink small outline package [tssop] ru-20 ad5331bruz-reel7 1 C40c to +105c 20-lead thin shrink small outline package [tssop] ru-20 ad5340bru C40c to +105c 24-lead thin shrink small outline package [tssop] ru-24 ad5340bru-reel C40c to +105c 24-lead thin shrink small outline package [tssop] ru-24 ad5340bru-reel7 C40c to +105c 24-lead thin shrink small outline package [tssop] ru-24 ad5340bruz 1 C40c to +105c 24-lead thin shrink small outline package [tssop] ru-24 ad5340bruz-reel 1 C40c to +105c 24-lead thin shrink small outline package [tssop] ru-24 ad5340bruz-reel7 1 C40c to +105c 24-lead thin shrink small outline package [tssop] ru-24 ad5341bru C40c to +105c 20-lead thin shrink small outline package [tssop] ru-20 ad5341bru-reel C40c to +105c 20-lead thin shrink small outline package [tssop] ru-20 ad5341bru-reel7 C40c to +105c 20-lead thin shrink small outline package [tssop] ru-20 ad5341bruz 1 C40c to +105c 20-lead thin shrink small outline package [tssop] ru-20 ad5341bruz-reel 1 C40c to +105c 20-lead thin shrink small outline package [tssop] ru-20 ad5341bruz-reel7 1 C40c to +105c 20-lead thin shrink small outline package [tssop] ru-20 1 z = rohs compliant part.
ad5330/ad5331/ad5340/ad5341 rev. a | page 26 of 28 notes
ad5330/ad5331/ad5340/ad5341 rev. a | page 27 of 28 notes
ad5330/ad5331/ad5340/ad5341 rev. a | page 28 of 28 notes ?2000C2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d06852-0-2/08(a)

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